EP93XX. ARM. ®. 9 Embedded Processor Family. EP93xx. User’s Guide 8×8 Key Mtx. ARMT. Maverick. 18 Bit Raster. LCD I/F. Crunch. Notes on making a proper EABI cross compiler for Maverick Crunch (EP, EP93xx) processors. This is a bit of “higher order hacking” and. It’s already configured to build in /opt/toolchains/ directory. This work is based on patches by Martin Guy and tested both on Cirrus demo board for the EP
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The ARMT’s bit microcontroller architecture, with a five-stage pipeline, delivers impressive performance at very low power. Voice, Record, Control, and Playback. Under Linux on the sample board I use, forward is disabled by default.
Thus, to use it efficiently, integer and floating point instructions must be interleaved so as to keep both processors busy. For applications with instruction-memory size restrictions, the ARMT’s compressed Thumb instruction set provides space efficiency and maximum external instruction memory usage.
The EP is a high-performance system-on-chip design that includes a MHz ARM9 processor and is ideal for a range of industrial and consumer electronic applications. The rich set of peripherals natively implemented by the microprocessor allow the module to drive all kind of buses commonly used in the industrial and PC worlds: It appears as co-processors 4, 5 and 6 and its instruction words in hexadecimal match the regular expression 0x.
A test program tickles the bug in both ways on revision E1 silicon. The bugs The bugs are: The software workaround involves avoiding a pair of consecutive instructions with these properties. Module Height and Width. Zefeer Environmental Test Report.
Software and Tools Software and Design Resources available by request. There is a long description of it at http: Block Diagram View Full Image. In GCC output, this is further restricted to 0xe[cde] ArmEabiMaverickCrunch last modified These operations can only be done between Maverick registers, but data can be copied between Maverick and ARM registers and between Maverick registers and main memory. When the error occurs, the result is either coprocessor register or memory corruption.
Obviously you need to get the unwind specification in the official ARM EABI documents first before implementing it in GCC, and binutils will also need to support generating correct information given. Let the immediately following instruction be a two-word coprocessor load or store. The above patch incorrectly calls the iWMMXt pop functions. Sign is preserved properly, however.
[linux-cirrus] I’m pretty close with Maverick Crunch on EP – linux-cirrus – FreeLists
Eo9302 forwarding in a test program on revision E1 hardware, I have been unable to get this bug to bite. If there are serialized ones out there, GCC does not emit conditional Maverick instructions, which just leaves the case of a Maverick instruction being in one of the two slots after a branch that is taken, which is covered by -mcirrus-fix-invalid-insns.
crosstool-ng for the Maverick Crunch processors
GCC does not use: By enabling or disabling the EP’s peripheral interfaces, designers can also reduce development costs and accelerate time to market by creating a single platform that can be modified to deliver differentiated end-products. Characteristics and naming are summarized in the document ZefeerEVB.
The unpublished futaris patches for 4. For further information about the Kit and the usage, please dp9302 sales dave.
Chip house supports Linux on new ARM-based offering
Futaris and Cirrus remove this flag. Given that any resulting denormalised numbers will probably be truncated to zero by the math ops in bug 12a, there may be not be much point in doing this. Skip to main content. An instruction may be nonexecuted because it is conditional and the condition is false, e. Designers of industrial controls, internet radios, digital media servers, audio jukeboxes, thin clients, set-top boxes, point-of-sale terminals, biometric security systems and GPS devices will benefit from the EP’s integrated architecture and advanced features.
The ARMT core operates from a 1. Zefeer specific integration guidelines.
The value appearing in the target register will still be correct. This could already be handled by faking a 63 bit truncation and using a splitter to expand those into something like this I only know integer ARM assembly, so I’m making this up: The sign is unaffected. It has a different instruction set from other floating point accelerators that are found with ARM processors: Do not depend on the sign extension to occur; that is, ignore the upper word in any calculations involving data loaded using these instructions.
Cirrus Logic’s embedded processor products are complemented by a range of complete operating systems. The Cirrus crunch softfloat library has integer asm code to check for denorm values before these operations e. Here we only attempt to work around the bugs in the later series. The kit is composed by: It has its own instruction set which performs floating point addition, subtraction, multiplication, negation, absolute value, and comparisons as well as addition, multiplication and bit shifts on integers.
A new Pop MV registers instruction needs to be added to the table, along with changes to Sec 7. Single-precision floats live in the top 32 bits of the register and, when they are written, the lower 32 bits are zeroed. These include all of the following: Some real-life programs compiled with it do seem to work though.
It also has four bit multiply-accumulate integer registers which are not used by GCC. Unfortunately these never worked well enough for it to be usable.